The formation of non-isotropic patterns (i.e., essentially vertical etch profiles) on the surface of silicon wafers is essential when the thickness of the film being etched is comparable to the minimum pattern dimensions of the to-be-formed features. For example, in very large scale integration (VLSI) devices, many of the films have thickness on the order of about 0.5 to 1 microns (.mu.m) whereas the to-be-formed patterns are on the order of about 1 to 2 .mu.m. Accordingly, undercutting which accompanies typical isotropic etching methods (e.g., wet etching) becomes intolerable at these dimensions. See, for example, Wolf, "Silicon Processing for the VLSI Era", Vol. 1, Chapter 16 ("Dry Etching for VLSI Fabrication"), Lattice Press, Sunset Beach, Calif. (1986).
In view of the above, dry non-isotropic etching procedures have been developed to transfer such patterns onto silicon wafers including, by way of example, reactive ion etching, reactive ion beam etching, electron beam etching, plasma etching, and the like. Common to such dry non-isotropic etching procedures is the use of a reaction chamber wherein the silicon wafer to be etched is placed in a wafer holder. In addition to holding the wafer, the wafer holder is also used to maintain a constant wafer temperature which, among other factors, is important to ensure constant etch rates on the wafer. Typically, the wafer is maintained between -20.degree. and 60.degree. C. during dry non-isotopic etching and, if the wafer temperature is uneven over its surface, then areas of the wafer which are at higher temperatures will tend to etch faster then areas of the wafer maintained at lower temperatures. In turn, uneven etch rates can provide for undesirable uneven patterning which can reduce the degree of non-isotropic etching.
Suitable wafer holders include electrodes (which can impart a low level of heat to the wafer to maintain constant wafer surface temperatures); inert materials (which can act as a heat sink during non-isotropic etching to maintain constant wafer surface temperatures); and the like. In general, a stream of helium gas is permitted to flow to the backside of the wafer holder (the surface of the holder opposite the wafer) to further ensure constant wafer temperature which procedure is referred to as "backside cooling".
Notwithstanding the advantages of dry non-isotropic etching, serious problems with underetching and particulate formation are encountered when such etching is employed to remove polycides from the wafer surface. Specifically, refractory metal polycides (e.g., tungsten silicide (WSi.sub.2), molybdenum silicide (MoSi.sub.2), and the like) are employed at numerous sites of the to-be-formed circuits elements including, by way of example, metal interconnect technology, Si-gate technology, and the like, because such silicides have lower resistance, i.e., sheet resistance, as compared to polysilicon. In turn, lower sheet resistance permits the semiconductor device to be operated under faster real time conditions thereby enhancing the operating speed of the device.
In forming a layer of refractory metal polycide on the surface of such circuit elements, a layer of refractory metal or refractory metal silicide is first deposited over the entire surface of the wafer. When a refractory metal is deposited, the metal is then converted to a metal silicide by conventional methods such as thermal annealing. In either case, a layer of resist is then patterned over the surface of the wafer so as to define the to-be-formed circuit elements containing a surface of metal silicide. Next, the wafer surface is subjected to dry non-isotropic etching so as to remove the metal silicide in all areas except under the resist. Upon removal of the resist layer, a surface layer of metal silicide is found only at the desired circuit features.
It has been found, however, that the dry non-isotropic etching of the metal silicide layer on the surface of a silicon wafer utilizing backside cooling results in underetching of the wafer coupled with gross residues across the wafer surface. Both phenomena are severely deleterious to the effectiveness of the etch process as well as the wafer produced thereby. Specifically, underetching of the wafer surface and particulate contamination on the surface of the wafer can alter the functionality of the to-be-formed circuit elements.
The basic sequence of steps involved in the formation of a metal-to-silicon contact structure for an integrated circuit comprises the steps of:
Forming heavily doped regions which extend relatively deeply into the silicon in locations where contacts are to be established;
forming a thermal oxide or CVD-oxide layer on the surface of the fabricated or partially fabricated integrated circuit device;
etching a window, or contact hole, in the silicon-oxide layer by wet or dry etching techniques;
cleaning the silicon surface to remove any native oxide-layer that is known to rapidly form on a silicon surface when it is exposed to an oxygen-containing ambient;
depositing a metal film on the surface which makes contact with the silicon wherever contact holes have been created in the oxide, the deposited metal is typically aluminum or an aluminum alloy; and
subjecting the contact structure to a thermal cycle known as sintering or annealing to bring the metal and silicon surfaces into intimate contact.
In the practice of this procedure, the art has sought and tried various procedures to insure that the deposited-metal films adequately cover the sidewalls of the contact windows without severe thinning, thereby achieving good-step coverage into the contact windows.
The formation of contact holes in the oxide that covers the wafer surface is a key step in the fabrication of contact structures. Two-step etch processes are often used in semiconductor processing to form contact and via holes in order to improve the aspect ratio of the hole for the subsequent deposition of metal. In conventional two-step etch processes, the first step typically consists of a wet chemical etch. The second step is typically an anisotropic plasma etch. Such a process is called a wet/dry etch. When the contact holes are larger than two microns, wet etching has often been used to open them. Even in such contact holes, however, wetting and reactant product removal can be a problem. To partially overcome the wetting problem and to insure better material flow into the vicinity of the reactant surface, mechanical or ultra-sound agitation was introduced. The isotropic nature of wet etching, however, made it ineffective for the patterning of smaller-sized contact holes. As a result, development of silicon oxide dry-etching processes had to be pursued. Alternatively, a dry-isotropic etch in a plasma-etch system is sometimes used in place of the wet-etch. Such a process is called a dry/dry etch. Dry etching, however, introduces a new set of problems including polymer contamination, damage of the silicon surface, and decrease of oxide etch rate with decrease in contact size. One consequence of the former effect was that either gases with less propensity for forming polymeric molecules would have to be found, or more complex processes to remove the polymers from the contact holes after etch would have to be developed. Dry etching also exhibited selectivity problems, which became more significant as junctions grew shallower.
In addition to the need to insure that the contact holes are opened and that silicon surface damage and contamination are minimized, it is also important to give the contact hole a shape that will result in good-step coverage by the metal that is deposited into it. In general, better step coverage will be obtained if the walls of the contact opening are sloped and the top corners are rounded. Several different approaches have been pursued to achieve these desired side-wall profiles.
The sidewall profile of a contact or via formed by conventional wet/dry or dry/dry etching has a sharp point where the isotopically etched film meets the anisotropically etched film. For small contacts of less than one micron in diameter, this can cause problems for metal step coverage in the contact or via, because the metal will tend to cusp at the sharp point and shadow any subsequent film deposition.
The sidewall profile is improved by smoothing the sharp point. This can be accomplished by high temperature reflow of the dielectric film. (However, this is not feasible if a metal such as aluminum has been deposited in a previous step, because of the low melting temperature of aluminum. Furthermore, such reflow may not be possible for sub-micron processes due to the limited thermal budget.) In reflow processes, wafers are exposed to a high temperature step after the contact holes have been opened. This causes the CVD doped-SiO.sub.2 layer to flow slightly, producing rounded corners and sloped sidewalls in the contact holes. Reference is made to S. Wolfe, "Silicon Processing For The VLSI Era", Volume 2,--"Process Integration", Lattice Press, Sunset Beach, Calif., 1990, pages 101-121, the contents of which is incorporated herein in its entirety as if fully set forth in ipsis verbis. This reference is hereinafter referred to as "Reference 1".
Reference 1 at page 105 reports other sidewall-contouring processes involving an etching procedure which are used to pattern the contact holes. The first of these uses a wet etch (which is isotropic) to partially etch the oxide, and follows this with anisotropic dry etch. The method yields a contact hole whose profile is sloped at the top but is vertical at the bottom. While good step coverage can be achieved in some applications, difficulty may be encountered in obtaining good wetting, especially for very small contacts. In addition, the side-wall profile still may have a sharp corner at the upper edge which gives rise to step-coverage problems. A variation of this method is to use a triple layer (oxide/nitride/oxide). The top oxide is wet etched to provide a sloped contact-hole sidewall, and the nitride serves as a etch stop. The remaining nitride and oxide are then etched with a vertical dry-etch step.
Another general approach involves the controlled erosion of photoresist that has been baked to produce a sloped photoresist wall. In this method, photoresist images of the contacts are exposed and developed using standard lithographic techniques. Following the development step, the resist images are subjected to a post development bake of approximately 150.degree. C. The resist flows during the bake, relaxing the vertical resist profile. Etching the resist and oxide at approximately the same rate replicates the tapered-resist profile onto the contact sidewall. While the bake-to-slope process is quite adequate for large contacts or vias greater than two microns in diameter, it is not easily scalable to smaller geometries. For such smaller contacts, resist baking steps become critical. Too little baking results in vertical contact profiles, while excessive baking can result in closed contacts. Furthermore, continued etching of the contact results in continued growth in the contact diameter.
Other more controllable resist-erosion techniques have subsequently been described. Another resist-erosion approach is reported at Reference 1, page 106. In this procedure, etching of the contact oxide is carried out with a photoresist mask that has vertical sidewalls. Oxygen is added to the CHF.sub.3 gases being used to etch the oxide. The oxygen attacks the resist at a controlled rate, thereby producing lateral as well as vertical etching of the resist mask. More of the top oxide is slowly exposed as vertical etching of the oxide proceeds, and a sloped oxide sidewall is produced. Taper angles of 40 to 85 degrees were obtained by varying the oxygen concentration.
A final group of processes utilize two or more dry-etch steps to obtain tapered-sidewall profiles. In one example, a high rate isotropic oxide etch is used to etch the top portion of the contact-oxide layer, and an anisotropic etch process is used to remove the oxide from the bottom of the contact hole.
In another method, a downflow etcher operated at 2.45 Gh.sub.z is used to etch part of a doped oxide layer in a isotropic manner using a CF.sub.4 plus O.sub.2 mixture, and this is followed by an RIE step to give a vertical profile for the bottom portion of the layer.
The problem of end-point detection for contact holes can also be difficult. That is, if a timed etch is used, a sufficient overetch must be allowed to insure that all the contacts are opened. However, this demands a high selectivity to the silicon to prevent too much silicon from being consumed during the overetch. End-point detection is difficult because the total area of the contacts being etched is significantly smaller compared to other layers.
Turning specifically to via fabrications, one aspect of minimum feature size that applies to via fabrication is the issue of the via sidewalls. For the same contact-opening sizes at the bottom of vias, straight sidewall vias would require less area than would those with sloped sidewalls. Furthermore, when dry etching is used to open the vias, it is often easier to produce straight rather than sloped sidewalls. Unfortunately, when physical vapor deposition is used to deposit the metal over the vias, straight sidewalls result in worse step coverage by the metal than if the sidewalls were sloped. The conclusion to be drawn is that in conventional via processing, sloped vias are necessary to ensure adequate step coverage in most applications when contact holes and vias are less than about 1.5 micron wide (Reference 1, pages 188-245, the disclosure of which has been incorporated herein by reference).
In summary, the conventional process sequence for the fabrication of contacts and vias, comprises the steps of: silicon oxide layer deposition; masking of the oxide layer with photoresist; the wet or dry isotropic etching of the oxide; a dry anisotropic etching of the oxide; the stripping of the photo resist; and the reflowing of the oxide layer in a thermal cycle.
In MOS applications, the gate length is a critical fine line dimension that determines the channel length of the device. Thus, when polysilicon serves as the gate material, it is paramount that the etched line width dimension faithfully reproduces the dimension on the mask to within plus or minus five percent (5%). A polysilicon etch process must therefore exhibit excellent line width control and high uniformity of etching. In addition, a high degree of anisotropy is also generally required, as the doping of the source and the drain, and the polysilicon itself, is typically performed by ion implantation. If the etch process produces sloped sidewalls in the polysilicon, or if the etching process produces lines of non-uniform width, then portions of the gate would not be thick enough to effectively mask the substrate against the implantation. This would produce devices whose channel length depended on the degree of sidewall taper and channel lengths would not be uniform from one device to another. Unless the taper can be accurately controlled and unless the critical dimension which is the channel length is uniform from device to device, there is a serious manufacturing control problem.
The degree of anisotropy, however, is dictated by other considerations as well, including the extent of overetching required to remove stringers at the base of steep steps in the underlying topography and the coverage of the etched polysilicon features by subsequently deposited layers. In the first of these cases, completely anisotropic etching will require extensive overetching to remove the stringers, while in the second, it will produce features that may be difficult for overlying films to cover. Thus, in general, an important characteristic of a process is its ability to produce a profile with the desired degree of slope with a small standard deviation in the critical dimension.
Finally, the polysilicon layer is usually deposited over thin silicon dioxide (e.g., gate oxides of about 80-500 A thickness). Thus, the etch process must be selective over oxide etching, since if this oxide layer were removed the shallow source-drain junction regions in the underlying silicon substrate would be rapidly etched by the reactants that cause polysilicon etching. In some cases, where buried contacts between polysilicon and the single crystal substrate are made, high selectivity over single crystal silicon must be exhibited.
Some proposed processes for etching polysilicon with all of the required etching parameters, involve multi-step etching processes.
Refractory metal silicides are deposited onto to polysilicon to form a low resistance polycide structure that can serve as both a gate and an interconnect layer. In many applications, etching is used to pattern such polycide structures, but this is a difficult etching task. As in polysilicon etching, the process must provide a vertical profile on the etched polycide, good selectivity over oxide (i.e., greater than 10), and a minimal resist erosion. Etching of refractory metal silicides with both fluorine and chlorine based plasmas has been investigated, as both the fluorides and chlorides of the refractory metals are relatively volatile. Etch gases that result in high concentrations of fluorine atoms, however, are not suitable, as they tend to undercut either the polysilicon or the silicide, or both. On the other hand, fluorine-deficient plasmas can produce anisotropic etching of both the polysilicon and the silicides.
In any event, it is reported that etch profiles vary widely with process parameters, especially the gas composition. As the silicide etch rates also vary with silicide composition, the successful implementation of a polycide etching process requires stringent process controls. In addition, it has been suggested that in order to achieve a polycide etch process that produces an appropriately-shaped polycide profile, together with high selectivity over silicon dioxide, a multi-step etch process may need to be employed.
It would be advantageous if a dry etching process parameter could be identified which controls the rate and uniformity of etching in thermal silicon dioxide layers, controls the taper of profiles etched into a silicon dioxide layer and controls the dimension and uniformity of etched structures in a polycide or polysilicon layer.